The present invention relates to vital processing systems, and particularly to a digital overspeed controller forming part of that larger system. An appreciation of the larger system can be gained by reference to co-pending applications Nos. 07/267,070 and 07/267,214, assigned to the assignee of the present invention, the details of the disclosures of which are incorporated herein by reference. In particular, FIG. 10 of Ser. No. 07/267,214 depicts the larger system in block form.
The invention is especially suitable for use in railway signalling and control systems which must be vital in their operation, that is, restricted to the safe or "off" state of each output which controls a signal, switch machine, or other signalling or control operation, unless the allowed or "on" condition thereof is enabled.
The present invention is an improvement in the subsystem or device known as a digital overspeed controller which forms part of a larger processing system and which, per se, has been known for the purpose of forming a variety of functions. One example of such a device is the governor disclosed in U.S. Pat. No. 4,495,578 assigned to the assignee of the present invention, the details of which disclosure are incorporated herein by reference.
In essence, the governor or governor means involved in U.S. Pat. No. 4,495,578 is responsive to a signal receiving means for receiving and registering wayside-imposed speed limits; it is also responsive to vehicle speed measuring means for imposing a braking force or a requirement for a braking operation on the vehicle if the vehicle speed is greater than the wayside-imposed speed limit, the improvement of that patent comprising the provision of speed profile generating means responsive to the signal receiving means for receiving a second speed limit at a time when a first, higher speed limit had been effective to generate a speed limit profile, the means for withholding application of the braking force, or the requirement therefor, being operative so long as the speed limit profile is generated and the vehicle speed is less than the current value of said speed limit profile.
In any event, all of the digital overspeed controllers known in the art are concerned with performing the following functions: interpreting the output pulses of a tachometer as speed and distance information; averaging the tachometer data to eliminate spurious "jumps" in speed, while retaining adequate speed response; reading manual wheel size" switches to determine wheel size; adjusting averaged speed information using wheel size to determine actual train speeds; inputting externally generated speed limit information; and determining if train speed is under the effective speed limit.
Although it has been known previously to employ the noted microprocessor-based speed governors, or over/underspeed controllers of one type or another, these have been so designed that the probability of a "wrong-side failure" has not had a calculable upper bound. Consequently, there is some degree of uncertainty or insecurity present in the operation of such previously known devices or subsystems.
Accordingly, it is a fundamental object of the present invention to provide a microprocessor-based digital overspeed controller which is so designed and constructed that the probability of a "wrong-side failure" has a calculable upper bound. Hence, one can be sure, within such statistical bound, that a combination of failures will not produce a real threat to vehicle safety.